Responsibilities:

• Develop and review verification plan
• Create testcase and perform RTL verification using SystemVerilog, UVM
• Debug the failing testcase, work with RTL design team analyze the root-cause
• Perform and evaluate verification regression
• Perform gate-level simulation with SDF back-annotation 
• Work in the RnD team to develop and validate for the high-bandwidth interface IP.
• Hands on experience in creating detailed Verification Environment from Functional Specifications
• Writing test cases, checkers, and doing coverage report.
• Debug of simulations, including those of real signals modeled using SV for analog.
• RTL, GLS & Co-simulations & coverage closure
• Take part in technical reviews, peer review.
• Follow and improve development process ensuring high quality output.

Requirements:

• BS/ MS/ PhD in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in Design Verification
• Familiar with design verification flow at IP or SoC level
• Experience in skill with design tools: VCS, Verdi. Familiar Formal verification tool (vc_formal) is a plus.
• Knowledge of SystemVerilog, UVM, and complex module testbench is a big plus
• Knowledge of Analog Mixed Signal design, High-Speed Interface IP is a big plus
• Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus.
• Accountable, result oriented and good English communication.
• Great team player, willing to support others.
• Self-motivated and enthusiasm in technology and problem solving.