Responsibilities:

• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
• Participate in building and enhancing layout flow for faster, higher quality design process.
• Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Do PERC verification for ESD/LUP checks
• Complete all design quality checks and data quality checks
• Work with Place and Route engineer to integrate analog layouts into top level.
• Work with Package team to ensure the integration of top die and package
• Do design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Work closely with design team in Viet Nam, USA, Canada and other countries to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full design block
• Mentor junior layout engineers or interns

Requirements:

• BS in Electronics Engineering, Electromechanics, Physics, Telecommunications.
• 2+ years of experience in custom layout.
• Familiar with Layout entry tools: Cadence,
• Familiar with Layout verification tools: Mentor Calibre, ICV
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
• Experienced with mentoring/leading junior layouts to complete a design.
• Experienced with writing layout review presentations and layout verification reports
• Good English communication
• Strong team player
• Self-motivated, humble, honest and willing to learn.