Job Description:

We are seeking a highly skilled and motivated   Physical Design Leader to join our team. The ideal candidate will lead a team of engineers to implement advanced-node physical design projects for cutting-edge semiconductor products. This role offers a unique opportunity to work on 5nm and 2nm technologies while contributing to the development of high-performance, low-power designs for network and consumer applications.

Responsibilities:

• Lead and mentor a team of Physical Design Engineers, providing technical guidance and support.
• Drive RTL-to-GDSII implementation, ensuring design quality, timing closure, power optimization, and area efficiency.
• Develop and execute   floor planning, placement, clock tree synthesis (CTS), and routing   strategies.
• Oversee Static Timing Analysis (STA), signal integrity checks, power integrity analysis, and EM/IR drop analysis.
• Implement and optimize power-aware design techniques using UPF/CPF methodologies.
• Collaborate with front-end design, verification, and DFT teams to ensure seamless integration and implementation.
• Work with foundries and EDA vendors to resolve tool-related challenges and enhance workflows.
• Develop automation scripts to improve design efficiency using TCL, Python, or Perl.
• Ensure designs meet DFM/DFT requirements and are compliant with manufacturing process constraints.
• Provide technical leadership in project execution, risk assessment, and mitigation strategies.

Requirements:

• A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field is required.
• 7+ years of experience in Physical Design  , with at least 2 years in a leadership role.
• Strong expertise in   advanced process nodes (7nm, 5nm, 3nm, 2nm).
• Hands-on experience with industry-standard tools such as Synopsys IC Compiler II (ICC2), Cadence Innovus, or Mentor Calibers  .
• Proficiency in Static Timing Analysis (STA) using Synopsys Primetime or equivalent tools.
• Deep understanding of clock tree synthesis (CTS), power optimization, and layout techniques.
• Experience in low-power design methodologies (UPF/CPF).
• Knowledge of signal integrity (SI), power integrity (PI), and DRC/LVS verification.
• Strong programming/scripting skills in   TCL, Python, Perl, or Shell scripting
• Excellent problem-solving skills, teamwork, and leadership capabilities.
• Effective communication skills in English.

Preferred Qualifications:

• Experience in 5nm or 2nm technology is a plus.
• Knowledge of chip-level integration and system-level considerations.
• Prior collaboration with foundries such as TSMC, Samsung, or GlobalFoundries.

Benefits:

• Competitive salary and performance-based bonuses are offered.
• Opportunity to work on cutting-edge semiconductor technologies.
• Professional work environment with clear career growth paths.
• Additional benefits based on performance.
• Full social insurance, health insurance, and travel policies.
• Training programs and support for international certifications.