Responsibilities:

• Design circuit for Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...
• Analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.
• Work closely with layout engineer to make sure layout quality. Perform post layout verifications.
• Perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.
• Design analysis and solve problems of noise, margin, signal integrity, power integrity.
• Complete all design quality checks and data quality checks
• Do design reviews across global team
• Work with digital/system engineer to integrate analog designs into mixed signal system.
• Perform mixed signal verification which combining both analog and digital blocks.
• Training for fresh engineers and interns.

Requirements:

• BS/ MS in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.
• Solid knowledge of CMOS Analog design knowledge and techniques
• Solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso
• Solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim…
• Good understanding of layout effects on circuit performance.
• Experienced with writing design review presentations and circuit verification reports
• Good English communication both verbally and in writing
• Great team player, willing to support others.
• Highly responsible, result oriented.
• Self-motivated and highly enthusiasm in technology and solving problems
• Leadership skill and experience is a plus
• Familiar with high speed analog designs, IO designs, PLL/DLL is a plus