Responsibilities:

• Do TOP simulation for big macro of a High Bandwidth Interface design including Power review, Circuit modeling and EMIR,…
• Analyze and verify design power and power network delivery to ensure the design to meet all requirements of performance and reliability.
• Work closely with IP design teams, Cover Cell teams to ensure the quality of layout for power, signals.
• Complete all check lists of the design quality and data quality.
• Do design reviews across global teams
• Training fresh engineers and interns

Requirements:

• BS/MS in Electronics Engineering, Electromechanics, Telecommunications.
• 2+ years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.
• Solid knowledge of CMOS Analog design knowledge and techniques.
• Solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso...
• Solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim (XA)…
• Good understanding of layout effects on circuit performance.
• Have experience with EMIR verification.
• Experienced with writing design review presentations and circuit verification reports.
• Good English communication both verbally and in writing.
• Great team player, willing to support others.
• Highly responsible, result oriented.
• Self-motivated and highly enthusiasm in technology and solving problems.
• Proficiency in using scripts: Cshell, Perl or Python is a plus.
• Leadership skill and experience is a plus.
• Familiar with high speed analog designs, IO designs, PLL/DLL is a plus.