Job Description:

- Responsible for cell layout, block level layout, macro planning and interconnect.
- Compact layout is essential.
- Working under designer’s supervision to keep schedule and quality intact.

Job Requirements:

- 4+ year’s analog/memory layout experience.

- BS or MS in Electrical Engineering. Semiconductor courses preferred.

- Hands-on 5 years plus in Semiconductor Integrated Circuit Layout Development.

- Fluency in Unix, other programming language.

- Fluency in mainstream CAD layout tools, skill works.

- Fluency in Vietnamese, English, others are plus.

- Professional ethic, team work.

- No restriction to any country with Microchip’s presence.

- Special skill in CAD system and IT is plus to support the layout team while the team size is small.