Responsibilities:

1. Develop and maintain verification environment for DUT using UVM with SystemVerilog.
2. Create and debug DUT test cases and Verification IP.
3. Write and review verification plan.
4. Use assertion based verification to verify module or SOC level.
5. Perform code coverage analysis on module and SOC level.
6. Report to Managing Mgr
7. Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.
8. As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.

Requirements:

1. Degree/Master in Electrical/Electronic Engineering.
2. Require 2 years or above experience in the area of digital IC verification.
3. Working experience from design to tapeout is essential.
4. Have outstanding debug capability.
5. Experience in SystemVerilog and UVM methodology.
6. Preferable have knowledge in USB, Ethernet, SPI, I2C, UART, graphics processor, microcontroller.